Sub-micron integrated circuits (ICs) require that the device surfaced be planarized at their metal inter-connect steps. Chemical mechanical polishing (CMP) is the technology of choice for planarizing wafer surfaces. The IC transistor packaging density has been doubled about every 18 months, according to the so called "Moore's Law".
There are two methods by which to increase the packing density of transistors on a chip. The first method is to increase the device or die size. This is not always the best method, however, because as the die size increases, the die yield per wafer decreases. Due to the fact that the defect density per unit area is the constraint factor, the amount of defect-free dies er area decreases as the die size increases. Not only will the yield be lower, but the number of die that can be stepped (printed) on the wafer will also decrease. The second method is to shrink the size of the transistor feature. Smaller transistors mean a higher switching speed. By decreasing the transistor size, more transistors and more logic functions or memory bits can be packed onto the same device area without increasing die size. The shrinking of the feature size is what has driven technology to deliver the results that were predicted by Dr. Moore of Intel.
Sub-half micron technology has been rapidly evolved into sub-quarter micron technology in the past three years alone. The number of transistors being fabricated on each chip has increased enormously--from hundreds of thousands transistors per chip three years ago to more than five million transistors per chip today, to hundreds of millions of transistors per chip by the year of 2006. By that time, the amount of inter-connect wiring will have increased from hundreds of meters in length today to more than 20 km. The current solution to the challenge is to build layers upon layers of inter-connect wiring with insulating (dielectric) thin films in between. The wiring is also connectable vertically through vies; to achieve all electrical paths as required by the integrated circuit functions.
A new technology which uses inlaid metal lines embedded in insulating dielectric layers was invented by IBM engineers in the late 80's to meet the I.C. inter-connect needs. The inlaid metal line structure allows for metal wiring connections to be made on the same plane as well as on an up and down direction through plasma etched trenches and vies in the dielectric layer. Theoretically, these connection planes can be built with as many layers on top of each other as desired, as long as each layer is well planarized with CMP process. The ultimate limit of the interconnect is formed by the connection resistance(R) and the proximity capacitance(C). The so-called RC constant limits the signal-to-noise ratio and causes the power consumption to increase, rendering the chop non-functional. According to the SIA road map forecasted for the year 2006, the number transistors to be integrated on a chip will be as many as one billion, and the number of layers of interconnect will increase from five layers to about nine layers.
To meet the new inter-connect technology challenge, the CMP process and CMP tool performance would desirably be improved to achieve the following three goals.
First, wafer edge exclusion due to over- and under-polishing must be reduced from 6 mm to less than 3 mm. It is necessary to increase the area of electrically good dies than can be produced around the peripheral area of the wafer. Due to the die size increase from 10 mm per side today to 20 mm per side, as well as the wafer size increase from 200 mm to 300 mm before the year 2006, the potential for electrically good dies will be more than double if the 2 mm edge exclusion CMP performance can be achieved.
Second, polishing non-uniformity would desirably be improved from 5% (1 sigma) to less than 3%. The wafer carrier design must be able to apply uniform and appropriate force across the wafer during polishing.
Third, CMP would desirably be capable of polishing metallized wafers under compressive or tensile stress. Commonly used metals for inter-connect are aluminum and copper alloy, titanium, titanium nitride, tungsten, tantalum, and copper. The metallized wafers are often under stress due to the process condition, hardness of the metal, or thickness of the metal. The stressed wafers can bow inward (compressive stress) or outward (tensile stress) and as a result can cause a serious non-uniformity problem during polishing, as metal line dishing and oxide or dielectric layer erosion occur. In both cases, the consequence is a yield loss or decrease in the number of good dies per wafer. The new improved floating head and floating retaining ring design will allow for polishing down forces to be distributed optimally across the entire wafer, the wafer edge, and onto the polishing pad prior to contacting the wafer edge, in order to achieve a uniformly planarized surface across the edge of the wafer and its interior.
Integrated circuits are conventionally formed on substrates, particularly silicon wafers, by the sequential deposition of one or more layers, which layers may be conductive, insulative, or semiconductive. These structures are sometimes referred to as the multi-layer metal structures (MIM's) and are important relative to achieving closepacking of circuit elements on the chip with the ever decreasing design rules.
Flat panel displays such as those used in notebook computers, personal data assistants (PDAs), cellular telephones, and other electronic devices, may typically deposit one or mor layers on a glass or other transparent substrate to form the display elements such as active or passive LCD circuitry. After each layer is deposited, the layer is etched to remove material from selected regions to create circuitry features. As a series of layers are deposited and etched, the outer or topmost surface of the substrate becomes successively less planar because the distance between the outer surface and the underlying substrate is greatest in regions of the substrate where the least etching has occurred, and the distance between the outer surface and the underlying substrate is least in regions where the greatest etching has occurred. Even for a single layer, the non-planar surface takes on an uneven profile of peaks and valleys. With a plurality of patterned layers, the difference in the height between the peaks and valleys becomes much more severe, and may typically vary by several microns.
A non-planar upper surface is problematic respective of surface photolithography used to pattern the surface, and respective of layers that may fracture if deposited on a surface having excessive height variation. Therefore, there is a need to planarize the substrate surface periodically to provide a planar layer surface. Planarization removes the non-planar outer surface to form a relatively flat, smooth surface and involves polishing away the conductive, semiconductive, or insulative material. Following planarization, additional layers may be deposited on the exposed outer surface to form additional structures including interconnect lines between structures, or the upper layer may be etched to form vias to structures beneath the exposed surface. Polishing generally and chemical mechanical polishing (CMP) more particularly are known methods for surface planarization.
The polishing process is designed to achieve a particular surface finish (roughness or smoothness) and a flatness (freedom from large scale typography). Failure to provide minimum finish and flatness may result in defective substrates, which in tern may result in defective integrated circuits.
During CMP, a substrate such as a semiconductor wafer, is typically mounted with the surface to be polished exposed, on a wafer carrier which is part of or attached to a polishing head. The mounted substrate is then placed against a rotating polishing pad disposed on a base portion of the polishing machine. The polishing pad is typically oriented such that it's flat polishing surface is horizontal to provide for even distribution of polishing slurry and interaction with the substrate face in parallel opposition to the pad. Horizontal orientation of the pad surface (the pad surface normal is vertical) is also desirable as it permits the wafer to contact the pad at least partially under the influence of gravity, and at the very least interact in such manner that the gravitational force is not unevenly applied between the wafer and the polishing pad. In addition to the pad rotation, the carrier head may rotate to provide additional motion between the substrate and polishing pad surface. The polishing slurry, typically including an abrasive suspended in a liquid and for CMP at least one chemically-reactive agent, may be applied to the polishing pad to provide an abrasive polishing mixture, and for CMP an abrasive and chemically reactive mixture at the pad substrate interface. Various polishing pads, polishing slurries, and reactive mixtures are known in the art, and which is combination allow particular finish and flatness characteristics to be achieved. Relative speed between the polishing pad and the substrate, total polishing time, and the pressure applied during polishing, in addition to other factors influence the surface flatness and finish, as well as the uniformity. It is also desirable that the polishing of successive substrates, or where a multiple head polisher is used, all substrates polished during any particular polishing operation are planarized to the same extent, including remove of substantially the same amount of material and providing the same flatness and finish. CMP and wafer polishing generally are well known in the art and not described in further detail here.
The condition of the polishing pad may also affect polishing results, particularly the uniformity and stability of the polishing operation over the course of a single polishing run, and more especially, the uniformity of polishing during successive polishing operations. Typically, the polishing pad may become glazed during one or more polishing operations as the result of heat, pressure, and slurry or substrate clogging. The effect is to lessen the abrasive characteristic of the pad over time as peaks of the pad are compressed or abraded and pits or voids within the pad fill with polishing debris. In order to counter these effects, the polishing pad surface must be conditioned in order to restore the desired abrasive state of the pad. Such conditioning may typically be carried out by a separate operation performed periodically on the pad to maintain its abrasive state. This also assists in maintaining stable operation during which a predetermined duration of polishing will remove a predetermined amount of material from the substrate, achieve a predetermined flatness and finish, and otherwise produce substrates that have sufficiently identical characteristics so that the integrated circuits fabricated from the substrates are substantially identical. For LCD display screens, the need for uniform characteristics may be even more pronounced, because unlike wafers which are cut into individual dies, a display screen which may be several inches across, will be totally unusable if even a small area is unusable due to defects.
An insert, as has conventionally been used is an inexpensive pad that is bonded to the wafer sub-carrier and is between the backside of the wafer and the carrier surface which may be a metal or ceramic surface. Variations in the mechanical characteristics of the insert typically may cause variations in the polishing results of CMP. Edge effects in the vicinity of the wafer periphery or edge may either degrade or alternately improve wafer surface characteristics depending on polisher head design. For example, on some polishing heads incorporating retaining rings, degrading effects may be lessened by providing an appropriate retaining ring structure to migrate the edge effects away from the wafer edge.
In U.S. Pat. No. 5,205,082 there is described a flexible diaphragm mounting of the sub-carrier having numerous advantages over earlier structures and methods, and U.S. Pat. No. 5,584,751 provides for some control of the down force on the retaining ring through the use of a flexible bladder; however, neither these patents describe structure for direct independent control of the pressure exerted at the interface of the wafer and retaining ring, or any sort of differential pressure to modify the edge polishing or planarization effects.
In view of the foregoing, there is a need for a chemical mechanical polishing apparatus which optimizes polishing throughput, flatness, and finish, while minimizing the risk of contamination or destruction of any substrate.
In view of the above, there remains a need for a polishing head that provides a substantially uniform pressure across the substrate surface being polished, that maintains the substrate substantially parallel to the polishing pad during the polishing operation, that maintains the substrate within the carrier portion of the polishing head without inducing undesirable polishing anomalies at the periphery of the substrate, and that desirably conditions the pad during the polishing operation.
The inventive structure and method incorporate numerous design details and innovative elements, some of which are summarized below. The inventive structures, methods, and elements are described in the detailed description.